1. Field of the Invention
The present invention relates to a display device and a method of driving the same, more particularly relates to a display device able to display images corresponding to a plurality of modes having different resolutions and a method of driving the same.
2. Description of the Related Art
Display devices, for example, liquid crystal display device using liquid crystal cells for display elements of pixels (electro-optical elements), are being used in a wide range of electronic devices, for example, personal digital assistants (PDA), mobile phones, digital cameras, video cameras, and personal computer display devices taking advantage of their characteristic features of thin shape and low power consumption.
FIG. 1 is a block diagram of an example of the configuration of a liquid crystal display device. A liquid crystal display device 1 has, as shown in FIG. 1, an effective pixel portion 2, a vertical drive circuit (VDRV) 3, and a horizontal drive circuit (HDRV) 4.
The effective pixel portion 2 has a plurality of pixel circuits 21 arranged in a matrix. Each pixel circuit 21 is constituted by a thin film transistor (TFT) 21 as a switching element, a liquid crystal cell LC 21 having a pixel electrode connected to a drain electrode (or a source electrode) of the TFT 21, and a storage capacitor Cs21 having one electrode connected to the drain electrode of the TFT 21. Corresponding to these pixel circuits 21, scan lines 5-1 to 5-m are arranged for every row along a pixel arrangement direction and signal lines 6-1 to 6-n are arranged for every column along the pixel arrangement direction. Gate electrodes of the TFTs 21 of the pixel circuits 21 are connected to the same scan lines 5-1 to 5-m in units of rows. Further, source electrodes (or drain electrodes) of the pixel circuits 21 are connected to the same signal lines 6-1 to 6-n in units of columns. In a general liquid crystal display device, a storage capacitor interconnect Cs is independently laid and storage capacitors Cs21 are formed between the storage capacitor interconnect and the connection electrodes. The storage capacitor interconnect Cs receives as input a same phase pulse as a common voltage VCOM. The other electrodes of the storage capacitors Cs21 of the pixel circuits 21 are connected to a supply line 7 of the common voltage VCOM inverting in polarity with every horizontal scan period (1H).
The scan lines 5-1 to 5-m are driven by the vertical drive circuit 3, while the signal lines 6-1 to 6-n are driven by the horizontal drive circuit 4.
The vertical drive circuit 3 performs processing for scanning in the vertical direction (row direction) every field period and successively selecting the pixel circuits 21 connected to the scan lines 5-1 to 5-m in units of rows. Namely, when the vertical drive circuit 3 gives the scan line 5-1 a scan pulse SP1, the pixels of the columns of the first row are selected, while when it gives the scan line 5-2 a scan pulse SP2, pixels of the columns of the second row are selected. In the same way after this, it successively gives the scan lines 5-3, . . . , 5-m the scan pulses SP3, . . . , SPm.
FIG. 2 is a circuit diagram of an example of the configuration of a vertical drive circuit of a general liquid crystal display device. Note that, in FIG. 2, a circuit for driving the odd number row (for example, the first row) scan line 5-1 and the next even number row (for example, the second row) scan line 5-2 is shown as an example.
This vertical drive circuit 3 has, as shown in FIG. 2, shift registers (S/R) 31 and 32 equipped with level shifters, sampling latches (EnbSML) 33 and 34, and negative power supply level shifters 35 and 36.
FIGS. 3A to 3F are timing charts of the circuit of FIG. 2. FIG. 3A shows a common voltage VCOM supplied to the other electrode of the storage capacitor Cs21 of each pixel PXL and having a polarity inverting for every horizontal scan period (1H); FIG. 3B shows a vertical clock VCK serving as a reference of the vertical scan; FIG. 3C shows an output signal S31 of the shift register 31; FIG. 4D shows an output signal S32 of the shift register 32; FIG. 4E shows an output signal S35 of the negative power supply level shifter 35; and FIG. 3F shows an output signal S36 of the negative power supply level shifter 36.
The shift registers 31 and 32 are supplied with a vertical start pulse VST instructing the start of a vertical scan and vertical clocks VCK and VCKX having inverse phases to each other and serving as references of a vertical scan generated by a not illustrated clock generator. For example, the vertical clock VCK is supplied to the shift registers 31 and 32 as a clock having an amplitude of 0-3.3V, but the shift registers 31 and 32 perform level shift operations from 3.3V to 7.3V. Further, the sampling latches 33 and 34 receive a common enable signal enb/xenb as shown in FIG. 2 and sample and latch the output signals S31 and S32 of the shift registers 31 and 32. Here, the periods where the adjacent scan lines are turned on and off are prevented from overlapping by setting a predetermined interval between a falling timing of the drive signal of a previous stage (odd number stage) and a rising timing of the drive signal of a latter stage (even number stage). The negative power supply level shifters 35 and 36 are connected to one end sides of the scan lines 5-1 and 5-2, receive the latch signals of the sampling latches 33 and 34, and successively supply the drive signals S35 and S36 as scan pulses of for example about 7.3V to the scan lines 5-1 and 5-2. Further, the negative power supply level shifters 35 and 36 supply the drive signals S35 and S36 level shifted from 0V to −4.8V to the scan lines 5-1 and 5-2 to reliably turn off the TFT 21 of the pixel circuit 221 at the time of non-selection. As shown in FIGS. 3A to 3F, in the horizontal scan period where the common voltage VCOM is a high level, the odd number row scan line 5-1 is driven, while in the horizontal scan period where the common voltage VCOM is a low level, the even number row scan line 5-2 is driven. In this way, for every horizontal scan period, the first row scan line 5-1 to the m-th row scan line 5-m are successively driven.
The horizontal drive circuit 4 is a circuit for level shifting selector pulses SEL and XSEL supplied by a not illustrated clock generator and write input a video signal into the pixel circuits line by line.
Further, a horizontal drive circuit in a liquid crystal display device using for example low temperature polycrystalline silicon, as shown in FIG. 4, is provided with a selector 8 having selector switches 81-R, 81-G, 81-B, . . . , 84-R, 84-G, 84-B, . . . , (8n-R, 8n-G, 8n-B), uses the selector switches to select data signals SDT1 to SDT4, . . . to be written into the pixel circuits 21, and supplies them to the signal lines 6-1 to 6-n to draw an image. A liquid crystal display device successively supplies the three primary color R (red) data, G (green) data, and B (blue) data to the signal lines, specifically, first supplies the R data to the signal lines 6-1 to 6-n, then supplies the G data to the signal lines 6-1 to 6-n, and finally supplies the B data to the signal lines 6-1 to 6-n to write them in the pixel circuits 21 and draw the images. Accordingly, each of the signal lines 6-1 to 6-n has three selector switches connected to it. FIG. 4 shows a state where only the selector switches 81-R to 84-R corresponding to R are turned on. When the R data finishes being written, only the selector switches 81-G to 84-G corresponding to G are turned ON and the G data is written. When the G data finishes being written, only the selector switches 81-B to 84-B corresponding to B are turned ON and the B data is written.
The selector switches 81-R, 81-G, 81-B, . . . , 84-R, 84-G, 84-B, . . . , (8n-R, 8n-G, 8n-B) of the selector 8 are configured by, as shown in FIG. 5, transfer gates TMG-R, TMG-G, and TMG-B connecting sources and drains of p-channel MOS (PMOS) transistors and n-channel MOS (NMOS) transistors. The transfer gates are controlled in conduction by select signals SEL1 and XSEL1, SEL2 and XSEL2, and SEL3 and XSEL3 taking complementary levels. Specifically, the transfer gates TMG-R configuring the R data selector switches 81-R to 84-R are controlled in conduction by the select signals SELL and XSEL1. The transfer gates TMG-G configuring the G data selector switches 81-G to 84-G are controlled in conduction by the select signals SEL2 and XSEL2. The transfer gates TMG-B configuring the B data selector switches 81-B to 84-B are controlled in conduction by the select signals SEL3 and XSEL3.
FIG. 6 is a view of an example of the configuration of the drive circuit of a transfer gate TMG(-R) of the selector 8. This transfer gate drive circuit 9 is configured by a level shifter 91 for shifting the levels of the select signals SEL and XSEL from an external circuit (IC) from −2.7V to 7.3V and buffers 92 and 93 connecting for example two CMOS inverters in series.
Summarizing the problem to be solved by the invention, in recent years, PDAs and other portable terminals have increasingly been required to mount high definition display panels, for example, display panels for display in a VGA mode (640×480) able to give a high definition image quality when viewing photographs or other graphic images.
When operating the above liquid crystal display device in the VGA mode, since the vertical drive circuit 3 only has outputs corresponding to the number of pixels one-to-one and has a fixed resolution, it is necessary to mount a vertical drive circuit corresponding to the VGA mode. However, a PDA etc. has many applications such as schedule management which do not require high definition display, for example, where display in the QVGA mode (320×240) is sufficient. Regardless of this, it is necessary to drive it in the VGA mode having a high clock frequency at the time of operation, therefore power ends up being wastefully consumed.
Further, when realizing a liquid crystal display device of the VGA mode, the load in the panel, particularly the capacity and load of the signal lines, increases in comparison with the QVGA mode. Therefore, as shown in FIG. 6, it is necessary to enlarge the sizes of the transistors configuring the transfer gates serving as the selector switches of the selector 8 of the horizontal drive circuit 4 and enlarge sizes of the transistors configuring the buffers 92 and 93 of the transfer gate drive circuit 9 to enlarge the driving capability. In this case as well, however, in the same way as the vertical drive circuit, despite a PDA etc. having many applications such as schedule management which do not require high definition display, for example, where display in the QVGA mode (320×240) is sufficient, use is made of transfer gates and buffers having transistor sizes enlarged in the driving capability so as to handle the VGA mode, so power ends up being wastefully consumed.